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1 ? fn9072.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2004. all rights reserved. all other trademarks mentioned are the property of their respective owners. hip6601b, hip6603b, hip6604b synchronous rectified buck mosfet drivers the hip6601b, hip6603b and hip6604b are high- frequency, dual mosfet drivers specifically designed to drive two power n-channel mosfets in a synchronous rectified buck converter topology. these drivers combined with a hip63xx or the isl65xx series of multi-phase buck pwm controllers and mosfets form a complete core- voltage regulator solution for advanced microprocessors. the hip6601b drives the lower gate in a synchronous rectifier to 12v, while the upper gate can be independently driven over a range from 5v to 12v. the hip6603b drives both upper and lower gates over a range of 5v to 12v. this drive-voltage flexibility provid es the advantage of optimizing applications involving trade-of fs between switching losses and conduction losses. the hip6604b can be configured as either a hip6601b or a hip6603b. the output drivers in the hip6601b, hip6603b and hip6604b have the capacity to efficiently switch power mosfets at frequencies up to 2mhz. each driver is capable of driving a 3000pf load with a 30ns propagation delay and 50ns transition time. these products implement bootstrapping on the upper gate with only an external capacitor required. this reduc es implementation complexity and allows the use of higher pe rformance, cost effective, n-channel mosfets. adaptive shoot-through protection is integrated to prevent both mosfets from conducting simultaneously. features drives two n-channel mosfets adaptive shoot-through protection internal bootstrap device supports high switching frequency - fast output rise time - propagation delay 30ns small 8 ld soic and epsoic and 16 ld qfn packages dual gate-drive voltages for optimal efficiency three-state input for output stage shutdown supply undervoltage protection qfn package - compliant to jedec pub95 mo-220 qfn?quad flat no leads?product outline. - near chip-scale package footprint; improves pcb efficiency and thinner in profile. pb-free available as an option applications core voltage supplies for intel pentium? iii, amd? athlon? microprocessors high frequency low profile dc-dc converters high current low voltage dc-dc converters related literature technical brief tb363, guidelines for handling and processing moisture sensitive surface mount devices (smds) data sheet july 2004 n ot r e c o m m e n d e d f o r n e w d e s i g n s i n t e r s i l r e c o m m e n d s : i s l 6 6 1 2 , i s l 6 6 1 2 a , i s l 6 6 1 3 , i s l 6 6 1 3 a , i s l 6 6 1 4 , i s l 6 6 1 4 a
2 pinouts hip6601bcb, hip6603bcb (soic) hip6601ecb, hip6603ecb (epsoic) top view hip6604b (qfn) top view ordering information part number temp. range (c) package pkg. dwg. # hip6601bcb 0 to 85 8 ld soic m8.15 hip6601bcb-t 8 ld soic tape and reel hip6601bcbz (see note) 0 to 85 8 ld soic (pb-free) m8.15 hip6601bcbz-t (see note) 8 ld soic tape and reel (pb-free) hip6601bcbza (see note) 0 to 85 8 ld soic (pb-free) m8.15 hip6601bcbza-t (see note) 8 ld soic tape and reel (pb-free) hip6601becb 0 to 85 8 ld epsoic m8.15b hip6601becb-t 8 ld epsoic tape and reel hip6601becbz (see note) 0 to 85 8 ld epsoic (pb-free) m8.15b HIP6601BECBZ-T (see note) 8 ld epsoic tape and reel (pb-free) hip6603bcb 0 to 85 8 ld soic m8.15 hip6603bcb-t 8 ld soic tape and reel hip6603bcbz (see note) 0 to 85 8 ld soic (pb-free) m8.15 hip6603bcbz-t (pb-free) 8 ld soic tape and reel (pb-free) hip6603becb 0 to 85 8 ld epsoic m8.15b hip6603becb-t 8 ld epsoic tape and reel hip6603becbz (see note) 0 to 85 8 ld epsoic (pb-free) m8.15b hip6603becbz-t (see note) 8 ld epsoic tape and reel (pb-free) hip6604bcr 0 to 85 16 ld 4x4 qfn l16.4x4 hip6604bcr-t 16 ld 4x4 qfn tape and reel hip6604bcrz (see note) 0 to 85 16 ld 4x4 qfn (pb-free) l16.4x4 hip6604bcrz-t (see note) 16 ld 4x4 qfn tape and reel (pb-free) note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase pvcc vcc lgate 1 3 4 15 nc boot pwm gnd ugate nc phase nc 16 14 13 2 12 10 9 11 6 578 nc pvcc lv c c vcc pgnd nc lgate nc hip6601b, hip 6603b, hip6604b
3 block diagrams hip6601b and hip6603b hip6604b qfn package pvcc vcc pwm +5v 10k 10k control logic shoot- through protection boot ugate phase lgate gnd ? vcc for hip6601b ? pvcc for hip6603b for hip6601ecb and hip6603ecb devices, the pad on the bottom pa d side of the package must be soldered to the pc board. pvcc vcc pwm +5v 10k 10k control logic shoot- through protection boot ugate phase lgate pgnd lv c c connect lvcc to vcc for hip6601b configuration gnd pa d pad on the bottom side of the package must be soldered to the pc board connect lvcc to pvcc for hip6603b configuration. hip6601b, hip 6603b, hip6604b
4 typical application: 3-channel converter using hi p6301 and hip6601b gate drivers +5v boot ugate phase lgate pwm vcc +12v +5v boot ugate phase lgate pwm vcc pvcc drive +12v +5v boot ugate phase lgate pwm vcc +12v +v core pgood vid fs gnd isen3 isen2 isen1 pwm3 pwm2 pwm1 vsen main vfb vcc +5v comp hip6601b control hip6301 pvcc drive hip6601b pvcc drive hip6601b hip6601b, hip 6603b, hip6604b
5 absolute maximum ratings supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.3v boot voltage (v boot - v phase ). . . . . . . . . . . . . . . . . . . . . . . .15v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate . . . . . . . v phase - 5v(<400ns pulse width) to v boot + 0.3v . . . . . . . . . . . . v phase -0.3v(>400ns pulse width) to v boot + 0.3v lgate . . . . . . . . . gnd - 5v(<400ns pulse width) to v pvcc + 0.3v . . . . . . . . . . . . . . gnd -0.3v(>400ns pulse width) to v pvcc + 0.3v phase. . . . . . . . . . . . . . . . . . gnd -5v(<400ns pulse width) to 15v . . . . . . . . . . . . . . . . . . . . . . .gnd -0.3v(>400ns pulse width) to 15v esd rating human body model (per mil-std-883 method 3015.7) . . . . .3kv machine model (per eiaj ed-4701 method c-111). . . . . . . .200v thermal information thermal resistance ja ( c/w) jc ( c/w) soic package (note 1) . . . . . . . . . . . . 97 n/a epsoic package (note 2). . . . . . . . . . 38 n/a qfn package (note 2). . . . . . . . . . . . . 48 10 maximum junction temperature (plastic package) . . . . . . . . 150 c maximum storage temperature range . . . . . . . . . . . -65 c to 150 c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 c (soic - lead tips only) for recommended soldering conditions see tech brief tb389. operating conditions ambient temperature range. . . . . . . . . . . . . . . . . . . . . 0 c to 85 c maximum operating junction temperature . . . . . . . . . . . . . . 125 c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v 10% supply voltage range, pvcc . . . . . . . . . . . . . . . . . . . . . 5v to 12v caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high effective thermal conducti vity test board with ?direct attach? fe atures. jc, the ?case temp? is measured at the center of the expos ed metal pad on the package underside. see tech brief tb379. electrical specifications recommended operating conditions, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc hip6601b, f pwm = 1mhz, v pvcc = 12v - 4.4 6.2 ma hip6603b, f pwm = 1mhz, v pvcc = 12v - 2.5 3.6 ma upper gate bias current i pvcc hip6601b, f pwm = 1mhz, v pvcc = 12v - 200 430 a hip6603b, f pwm = 1mhz, v pvcc = 12v - 1.8 3.3 ma power-on reset vcc rising threshold 9.7 9.95 10.4 v vcc falling threshold 7.3 7.6 8.0 v pwm input input current i pwm v pwm = 0v or 5v (see block diagram ) - 500 - a pwm rising threshold 3.45 3.6 - v pwm falling threshold - 1.45 1.55 v ugate rise time t rugate v pvcc = 12v, 3nf load - 20 - ns lgate rise time t rlgate v pvcc = 12v, 3nf load - 50 - ns ugate fall time t fugate v pvcc = 12v, 3nf load - 20 - ns lgate fall time t flgate v pvcc = 12v, 3nf load - 20 - ns ugate turn-off propagation delay t pdlugate v pvcc = 12v, 3nf load - 30 - ns lgate turn-off propagation delay t pdllgate v pvcc = 12v, 3nf load - 20 - ns shutdown window 1.4 - 3.6 v shutdown holdoff time - 230 - ns output upper drive source impedance r ugate v pvcc = 5v - 1.7 3.0 ? v pvcc = 12v - 3.0 5.0 ? upper drive sink impedance r ugate v pvcc = 5v - 2.3 4.0 ? v pvcc = 12v - 1.1 2.0 ? lower drive source current equivalent drive source impedance i lgate r lgate v pvcc = 5v 400 580 - ma v pvcc = 12v 500 730 - ma v pvcc = 5v - 9 - ? lower drive sink impedance r lgate v pvcc = 5v or 12v - 1.6 4.0 ? hip6601b, hip 6603b, hip6604b
6 functional pin description ugate (pin 1), (pin 16 qfn) upper gate drive output. connect to gate of high-side power n-channel mosfet. boot (pin 2), (pin 2 qfn) floating bootstrap supply pin for the upper gate drive. connect a bootstrap capacitor between this pin and the phase pin. the bootstrap capaci tor provides the charge to turn on the upper mosfet. a resistor in series with boot capacitor is required in certain applications to reduce ringing on the boot pin. see the internal bootstrap device section under description for guidance in choosing the appropriate capacitor and resistor values. pwm (pin 3), (pin 3 qfn) the pwm signal is the control input for the driver. the pwm signal can enter three distinct st ates during operation, see the three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. gnd (pin 4), (pin 4 qfn) bias and reference ground. all signals are referenced to this node. pgnd (pin 5 qfn package only) this pin is the power ground return for the lower gate driver. lgate (pin 5), (pin 7 qfn) lower gate drive output. connect to gate of the low-side power n-channel mosfet. vcc (pin 6), (pin 9 qfn) connect this pin to a +12v bias supply. place a high quality bypass capacitor from this pin to gnd. lvcc (pin 10 qfn package only) lower gate driver supply voltage. pvcc (pin 7), (pin 11 qfn) for the hip6601b and the hip6604b, this pin supplies the upper gate drive bias. connect this pin from +12v down to +5v. for the hip6603b, this pin supplies both the upper and lower gate drive bias. connect this pin to either +12v or +5v. phase (pin 8), (pin 14 qfn) connect this pin to the source of the upper mosfet and the drain of the lower mosfet. the phase voltage is monitored for adaptive shoot-t hrough protection. this pin also provides a return path for the upper gate drive. description operation designed for versatility and speed, the hip6601b, hip6603b and hip6604b dual mosfet drivers control both high-side and low-side n-channel fets from one externally provided pwm signal. the upper and lower gates are held low until the driver is initialized. once the vcc voltage surpasses the vcc rising threshold (see electrical specifications ), the pwm signal takes control of gate transitions. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram ). after a short propagation delay [t pdllgate ], the lower gate begins to fall. typical fall times [t flgate ] are provided in the electrical specifications section. adaptive shoot-through circuitry monitors the lgate voltage and determines the upper gate delay time [t pdhugate ] based on how quickly the lgate voltage drops below 2.2v. this prevents both the lower and upper mosfets from conducting simultaneously or shoo t-through. once this delay period is complete the upper gate drive begins to rise [t rugate ] and the upper mosfet turns on. timing diagram pwm ugate lgate t pdllgate t flgate t pdhugate t rugate t pdlugate t fugate t pdhlgate t rlgate hip6601b, hip 6603b, hip6604b
7 a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlugate ] is encountered before the upper gate begins to fall [t fugate ]. again, the adaptive shoot- through circuitry determines the lower gate delay time, t pdhlgate . the phase voltage is monitored and the lower gate is allowed to rise after phase drops below 0.5v. the lower gate then rises [t rlgate ], turning on the lower mosfet. three-state pwm input a unique feature of the hip660x drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 2.2v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the phase voltage during ugate turn-off. once phase has dropped below a threshold of 0.5v, the lgate is allowed to rise. phase continues to be monitored during the lower gate rise time. if phase has not dropped below 0.5v within 250ns, lgate is taken high to keep the bootstrap capacitor charged. if the phase voltage exceeds the 0.5v threshold during this period and remains high for longer than 2 s, the lgate transitions low. both upper and lower gates are then held low unt il the next rising edge of the pwm signal. power-on reset (por) function during initial startup, the vcc voltage rise is monitored and gate drives are held low until a typical vcc rising threshold of 9.95v is reached. once the rising vcc threshold is exceeded, the pwm input signal takes control of the gate drives. if vcc drops below a typical vcc falling threshold of 7.6v during operation, then both gate drives are again held low. this condition persists until the vcc voltage exceeds the vcc rising threshold. internal bootstrap device the hip6601b, hip6603b, and hi p6604b drivers all feature an internal bootstrap device. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor must have a maximum voltage rating above vcc + 5v. the bootstrap capacitor can be chosen from the following equation: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose a huf76139 is chosen as the upper mosfet. the gate charge, q gate , from the data sheet is 65nc for a 10v upper gate drive. we will assume a 200mv droop in drive voltage over the pwm cycle. we find that a bootstrap capacit ance of at least 0.325 f is required. the next larger standard value capacitance is 0.33 f. in applications which require down conversion from +12v or higher and pvcc is connected to a +12v source, a boot resistor in series with the boot capacitor is required. the increased power density of these designs tend to lead to increased ringing on the boot and phase nodes, due to faster switching of larger currents across given circuit parasitic elements. the addition of the boot resistor allows for tuning of the circuit until the peak ringing on boot is below 29v from boot to gnd and 17v from boot to vcc. a boot resistor value of 5 ? typically meets this criteria. in some applications, a well tuned boot resistor reduces the ringing on the boot pin, but the phase to gnd peak ringing exceeds 17v. a gate resistor placed in the ugate trace between the controller and upper mosfet gate is recommended to reduce the ringing on the phase node by slowing down the upper mosfet turn-on. a gate resistor value between 2 ? to 10 ? typically reduces the phase to gnd peak ringing below 17v. gate drive voltage versatility the hip6601b and hip6603b provide the user total flexibility in choosing the gate drive voltage. the hip6601b lower gate drive is fixed to vcc [+12v], but the upper drive rail can range from 12v down to 5v depending on what voltage is applied to pvcc. the hip6603b ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc will set both driver rail voltages. power dissipation package power dissipation is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125c. the maximum allowable ic power dissipation for the so8 package is approximately 800mw. when designing the driver into an application, it is recommended that the following calculation c boot q gate ? v boot ----------------------- - hip6601b, hip 6603b, hip6604b
8 be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the driver is approximated as: where f sw is the switching frequency of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l is the upper and lower gate charge determined by mosfet selection and any external capacitance added to the gate pins. the i ddq v cc product is the quiescent power of the driver and is typically 30mw. the power dissipation approximation is a result of power transferred to and from the upper and lower gates. but, the internal bootstrap device also dissipates power on-chip during the refresh cycle. expressing this power in terms of the upper mosfet total gate charge is explained below. the bootstrap device conducts when the lower mosfet or its body diode conducts and pulls the phase node toward gnd. while the bootstrap device conducts, a current path is formed that refreshes the bootstrap capacitor. since the upper gate is driving a mosf et, the charge removed from the bootstrap capacitor is equivalent to the total gate charge of the mosfet. therefore, the refresh power required by the bootstrap capacitor is equivalent to the power used to charge the gate capacitanc e of the mosfet. where q loss is the total charge removed from the bootstrap capacitor and provided to the upper gate load. the 1.05 factor is a correction factor derived from the following characterization. the base circuit for characterizing the drivers for different loading profiles and frequencies is provided. c u and c l are the upper and lower gate load capacitors. decoupling capacitors [0.15 f] are added to the pvcc and vcc pins. the bootstrap c apacitor value is 0.01 f. in figure 1, c u and c l values are the same and frequency is varied from 50khz to 2mhz. pvcc and vcc are tied together to a +12v supply. curves do exceed the 800mw cutoff, but continuous operat ion above this point is not recommended. figure 2 shows the dissipation in the driver with 3nf loading on both gates and each individually. note the higher upper gate power dissipation which is due to the bootstrap device refresh cycle. again pvcc and vcc are tied together and to a +12v supply. test circuit the impact of loading on power dissipation is shown in figure 3. frequency is held constant while the gate capacitors are varied from 1nf to 5nf. vcc and pvcc are tied together and to a +12v supply. figures 4, 5 and 6 show the same characterization for the hip6603b with a +5v supply on pvcc and vcc tied to a +12v supply. since both upper and lower gate capacitance can vary, figure 8 shows dissipation curves versus lower gate capacitance with upper gate capac itance held constant at three different values. these curves apply only to the hip6601b due to power supply configuration. p1.05f sw 3 2 -- - v u q u v l q l + ?? ?? i ddq vcc + = p refresh 1 2 -- - f sw q loss v pvcc 1 2 -- - f sw q u v u == boot ugate phase lgate pwm pvcc gnd vcc 0.15 f 0.15 f 100k ? 2n7002 2n7002 0.01 f c l c u +5v or +12v +12v hip660x +5v or +12v figure 1. power dissipation vs frequency 1000 800 600 400 200 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 3nf vcc = pvcc = 12v c u = c l = 1nf c u = c l = 2nf c u = c l = 4nf c u = c l = 5nf figure 2. 3nf loading profile 1000 800 600 400 200 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 3nf vcc = pvcc = 12v c u = 3nf c u = 0nf c l = 0nf c l = 3nf hip6601b, hip 6603b, hip6604b
9 typical performance curves figure 3. power dissipation vs loading figure 4. power dissipation vs frequency (hip6603b) figure 5. 3nf loading profile (hip6603b) figure 6. variable loading profile (hip6603b) figure 7. power dissipation vs frequency (hip6601b) figure 8. power dissipation vs lower gate capacitance for fixed values of upper gate capacitance 1000 800 600 400 200 1.02.03.04.05.0 gate capacitance (c u = c l ) (nf) power (mw) 0 vcc = pvcc = 12v frequency = 1mhz frequency = 500khz frequency = 200khz 400 300 200 100 0 0 500 1000 1500 2000 frequency (khz) power (mw) vcc = 12v, pvcc = 5v c u = c l = 2nf c u = c l = 1nf c u = c l = 5nf c u = c l = 4nf c u = c l = 3nf vcc = 12v, pvcc = 5v c u = c l = 3nf c u = 3nf c u = 0nf c l = 0nf c l = 3nf 400 300 200 100 0 power (mw) 0 500 1000 1500 2000 frequency (khz) frequency = 500khz frequency = 1mhz vcc = 12v, frequency = 200khz pvcc = 5v frequency = 500khz 400 300 200 100 0 1.0 2.0 3.0 4.0 5.0 gate capacitance = (c u = c l ) (nf) power (mw) vcc = 12v, pvcc = 5v frequency = 1mhz frequency = 500khz frequency = 200khz 1000 600 400 200 0 1.0 2.0 3.0 4.0 5.0 power (mw) 800 gate capacitance (c u = c l ) (nf) 500 400 300 200 1.02.03.04.05.0 power (mw) lower gate capacitance (c l ) (nf) 100 vcc = 12v, pvcc = 5v frequency = 500khz c u = 5nf c u = 3nf c u = 1nf hip6601b, hip 6603b, hip6604b
10 hip6601b, hip 6603b, hip6604b small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15b 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.056 0.066 1.43 1.68 - a1 0.001 0.005 0.03 0.13 - b 0.0138 0.0192 0.35 0.49 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.31 3.39 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.64 6 n8 87 0 o 8 o 0 o 8 o - p - 0.094 - 2.387 11 p1 - 0.094 - 2.387 11 rev. 2 11/03 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are s hown for reference only. 9. the lead width ?b?, as measur ed 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.
11 hip6601b, hip 6603b, hip6604b quad flat no-lead plastic package (qfn) micro lead frame plast ic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
12 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hip6601b, hip 6603b, hip6604b small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93

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